Product Name: Switchtec™ Gen 6 PCIe® Switches

Manufacturer: Microchip Technology Inc.

Product Category: Communications & Networks

Supporting Documentation (if available)

In October 2025, Microchip Technology introduced its next generation of Switchtec™ Gen 6 PCIe® Switches, marking the industry’s first PCIe Gen 6 switches built on a 3 nm process. The Switchtec Gen 6 family is designed to reduce power consumption while supporting up to 160 lanes for high‑density AI system connectivity, and includes advanced security capabilities such as a hardware root of trust and secure boot, leveraging post‑quantum safe cryptography aligned with the Commercial National Security Algorithm Suite (CNSA) 2.0.

Built to address the data movement and scaling challenges of AI, high performance computing (HPC), and cloud data center architectures, the Switchtec PCIe Gen 6 family supports the PCIe 6.0 specification, doubling bandwidth versus PCIe 5.0 to 64 GT/s per lane using PAM4 signaling. This increase in throughput helps reduce interconnect bottlenecks between CPUs, GPUs, AI accelerators, and high performance storage, supporting better utilization of compute resources in heterogeneous systems.

The switch architecture is optimized for modern accelerator centric designs, enabling direct, low latency communication between devices. High lane density and non blocking performance allow system architects to build GPU dense platforms, composable infrastructure, and rack scale systems without relying exclusively on traditional CPU centric topologies. Support for PCIe 6.0 Flow Control Unit (FLIT) mode with Forward Error Correction (FEC) improves link efficiency and reliability, particularly for small, latency sensitive transactions common in AI and machine learning workloads.

Key product capabilities relevant to design engineers and system integrators include:
• Up to 160 PCIe Gen 6 lanes, configurable across as many as 20 ports with x16 and x8 bifurcation
• Non blocking switch fabric supporting full PCIe 6.0 bandwidth
• Hot plug and surprise plug controllers on every port to support serviceability and flexible system designs
• Non Transparent Bridging (NTB) for multi host and multi domain architectures with logical isolation
• Multicast support to enable efficient one to many data distribution within a PCIe domain

Reliability and error containment are central design considerations for Switchtec Gen 6 switches. Devices incorporate extensive protection mechanisms to help isolate faults and maintain system continuous operation in large scale deployments. These include Advanced Error Reporting (AER) on all ports, Downstream Port Containment (DPC) for isolating failing endpoints, and Completion Timeout Synthesis (CTS) to prevent upstream hosts from entering error states due to incomplete transactions. End to end data integrity is further supported through ECC protection on internal memory resources.

Security is integrated at the silicon level to address long system lifecycles and evolving threat models in data center environments. The inclusion of a hardware root of trust, secure boot, and CNSA 2.0 aligned post quantum cryptography, including ML DSA and ML KEM algorithms, allows platform designers to build systems aligned with emerging cryptographic standards without external security devices.

The Switchtec Gen 6 family also emphasizes design flexibility and ease of integration. A flexible reference clocking architecture with four input clocks per PCIe stack supports a wide range of system layouts. Integrated peripheral and management interfaces include I3C and SMBus compatible two wire interfaces, UARTs, GPIOs, and JTAG/EJTAG, for system monitoring and control. The switches support a broad ecosystem of PCIe cabling and connector options, including passive, managed, and optical cables, enabling deployment across diverse rack scale and chassis based systems.

To support development and deployment, the Switchtec Gen 6 switches are paired with Microchip’s ChipLink™ diagnostic and telemetry tools, providing engineers visibility into configuration, performance, and signal integrity through an intuitive graphical user interface. ChipLink supports both in band PCIe and sideband access paths, enabling comprehensive debug and analysis throughout the product lifecycle. An accompanying PCIe Gen 6 evaluation platform allows early validation and interoperability testing with server processors, accelerators, and storage devices.

The Switchtec PCIe Gen 6 Switch family is intended for use in AI and machine learning training clusters, hyperscale and cloud data centers, high performance storage fabrics, and other compute intensive environments requiring scalable bandwidth, high reliability, and built in security. By combining process node innovation, PCIe 6.0 performance, advanced error containment, and post quantum ready security, Microchip’s Switchtec Gen 6 switches deliver a powerful purpose built interconnect solution for next generation data center and AI infrastructure.